The present invention relates to an interfield interpolating apparatus having a vertical/horizontal motion compensating function, and particularly to an apparatus used in a MUSE decoder for a high definition television (HDTV), in which discordant pictures on interfields can be vertically and horizontally compensated when images wherein fields are moving in any direction, so that the pictures are in coincidence with each other.
In the instance where 1125 scanning lines constitute one frame in a MUSE television system, 562 scanning lines should be delayed to delay one field, for the purpose of interfield-interpolating. But, because the delaying amount in such a system is fixed at 562 scanning lines, the restored images at a receiver side represent the discordant pictures at the top and bottom portions thereof when the transmitted images at a transmitter side are moving in a vertical direction and, thus, creating a dimming phenomenon.
In order to eliminate this phenomenon, a vertical motion compensation should be implemented by a vertical motion vector corresponding to a vertical amount by which the images are moved the field. Accordingly, there is a need for a vertical compensating circuit to fulfill a such compensation.
In the conventional interfield interpolating apparatus, only a horizontal motion compensating function is provided. Thus, even though images at a transmitter side move in a horizontal direction, the apparatus can compensate the images in the same direction, thereby enabling them to be accurately signal-processed to obtain a clear still picture. However, if images at a transmitter side move in a vertical direction, the images which appear at a receiver side represent a discordant picture at top and bottom thereof because the apparatus has no a vertical motion compensating function.
In FIG. 1 which illustrates a known interfield interpolating apparatus, an image data is applied to serially connected delay circuits 1 and 2 via an input terminal IN. These delays 1 and 2 delay the received image data for a predeterminded interval and furnish it to a field delaying circuit 3 and a multiplexer 7, respectively. The delaying function which delays the received image data by as much as a fixed amount, such as 562 scanning lines is performed in the field delaying circuit 3. The delayed image data is again delayed by a period of one-horizontal scanning line in one-horizontal scanning line (1H) delay circuit 4. An adder 5 receives at its one terminal an output data of the field delaying circuit 3 and at its other terminal an output data of the 1H delay circuit 4, and performs an adding operation on the received data and provides the result to a pixel-delay circuit 6.
Then, pixel-delay circuit 6 compensates the result from the adder 5 by as much as the corresponding value of horizontal motion vector data from a control signal detector (not shown). At the same time, the horizontal motion vector data consists of 4 bits, making the compensating value between -8 to +7. A multiplexer 7 receives the outputs from the delay 2 and the pixel-delay circuit 6 and produces either one of the received outputs in accordance with a clock signal. Here, horizontal motion vector data and clock signal used in the conventional apparatus have a frequency which is 24.3 MHz.
In the configuration as described above, there is a problem in which since the field-delay circuit fixedly delays one field, i.e., 562 scanning lines, discordant images on interfields can not be compensated when images on field move in a vertical direction. Moreover, data transfer rate should be lowered in order to store a high-speed image data within a low-speed memory device.